1. Field of the Invention
The present invention relates in general to switched mode amplifier systems, and in particular to circuits and methods for current limiting under fault conditions, and slew rate control in switched mode amplifier systems.
2. Description of the Related Art
Class D audio power amplifiers (APAs) have been used for many years in systems, such as wireline telephony, where high bandwidth is not critical. More recently however, new fabrication techniques, and in particular, new techniques for fabricating power transistors, have made integrated class D APAs possible. This has extended their potential applications to lower-power, higher-bandwidth systems, including battery-powered portable music players and wireless communications devices.
One major advantage of class D amplifiers is their efficiency. Generally, an audio signal is converted into a relatively high frequency stream of pulses varying in width with the amplitude of the audio signal. This pulse width modulated (PWM) signal is used to switch a set of power output transistors between cutoff and saturation which results in efficiencies above ninety percent (90%). In contrast, the typical class AB push-pull amplifier, using output transistors whose conduction varies linearly during each half-cycle, has an efficiency of around sixty percent (60%). The increased efficiency of class D amplifiers in turn reduces power consumption and consequently lowers heat dissipation and improves battery life in portable systems.
As previously described, in a class D amplifier, efficiency is gained by switching the power devices hard between the power supply rails. The high frequency noise is then filtered with a low pass filter. Typically, the low pass filter is of the passive type, including inductive and/or capacitive reactive elements to smooth the signal. FIG. 1 illustrates, in block diagram form, a typical class D amplifier system 100. Amplifier system 100 includes class D amplifier 102 containing MOSFET switch 104 and PWM controller 106. PWM controller 106 receives a digitized audio input signal, which constitutes the signal to be amplified. MOSFET switch 104 may constitute a full bridge amplifier. The duty cycle of the PWM signal is proportional to the (quantized) amplitude of the audio signal. In other words, for each sample period, the relative time duration of the xe2x80x9chighxe2x80x9d and xe2x80x9clowxe2x80x9d levels of the PWM signal into MOSFET switch 106 are proportional to the quantized amplitude of the audio signal, and consequently the relative time intervals during which the output of the amplifier, ahead of LPF 110, is pulled up and pulled down is similarly proportional to the audio signal amplitude. In the subsequent discussion of a switched mode amplifier according to the principles of the present invention, the time interval within a sample period during which the PWM data is xe2x80x9chighxe2x80x9d and the output of the MOSFET switch (which may also be referred to as a driver) pulled up will be called the xe2x80x9chighxe2x80x9d phase, and conversely, the interval during which the PWM data is xe2x80x9clowxe2x80x9d, and the output concomitantly pulled down, will be referred to as the xe2x80x9clowxe2x80x9d phase. The amplified audio is recovered via low pass filter (LPF) 110, which provides the audio output to a load, Z.
System 100 provides overcurrent protection via a series resistence in the audio path. A short circuit or overload current is detected by monitoring the voltage across current limiting resistor 112. This voltage is fed back to PWM controller/driver 106. If the voltage across resistor 112 exceeds a predetermined threshold for a time interval that exceeds a predetermined length, PWM controller/driver 106 turns off the output transistors constituting switch 104. The presence of current limiting resistor 112 increases the inefficiency of system 100 as power is lost in the device, and moreover, the voltage across resistor 112 is difficult to detect in that resistor 112 is typically offset from ground, and the logic in PWM controller/driver 106 that detects the voltage across resistor 112 requires substantial common mode rejection.
According to the principles of the present invention, switched-mode amplifier current control apparatus is disclosed that includes a driver amplifier selectively configurable for operating in a first, second and third operating mode. Bias circuitry operable for limiting an output current of the driver amplifier is configured for selective coupling to the amplifier in the first operating mode. The driver amplifier is operable for transitioning from the first operating mode to a selected one of the second and third operating modes in response to a state of an output node of said driver amplifier.
The inventive concept addresses a problem in switched-mode drivers, namely, overcurrent detection and protection. Conventional switched-mode amplifiers employ a series resistance in the output node of the driver, and detect an overcurrent condition by monitoring the drop across the resistance. Power lost in the resistance decreases efficiency of the amplifier, and the offset of the resistance from ground complicates the measurement of the drop across the resistance. The bias circuitry limits the output current of the driver amplifier in the first operating mode. In accordance with a state of an output node of the driver amplifier, the amplifier is operable for transitioning to a selected one of the first and second operating modes.